INTEL's & AMD's Plan For New Quad Core Chips

On the chip level, AMD engineers added a shared Level 3 cache—an extra pool of memory used to store data close to the processor cores—to help feed data into the cores individual Level 2 caches. The L3 cache, which was designed to vary in size, can be accessed by any of the four cores. However, AMD engineers gave each processor core its own L2 cache on the grounds that sharing those caches can